1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to an interconnect process and a method for removing metal silicide.
2. Description of the Related Art
With great advancement in semiconductor fabrication technologies, dimensions of devices continue to shrink. When the level of integration increases, the surface area on a chip becomes insufficient to accommodate all interconnects. To meet the increase demands for interconnects with device miniaturization, a multi-layered design has been developed. In fact, most very large scale integrated (VLSI) circuit chips deployed a multi-layered interconnect design.
In the process of fabricating interconnects with a dimension smaller than 0.11 μm, a conventional etching operation using a photoresist layer as an etching mask can no longer produce a contact or conductive line with very small dimensions due to photolithographic limitations. Therefore, polysilicon with a high etching selectivity relative to the dielectric layer must be used as an etching mask. Because the metal in a metallic layer may react with silicon in the polysilicon at a high temperature, metal silicide layer is often formed on the surface of the polysilicon layer when polysilicon is used as an etching mask in the interconnect process. To facilitate subsequent fabrication processes, removing the silicide layer is a very important step.